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CD4047BMS
December 1992
CMOS Low-Power Monostable/Astable Multivibrator
Description
CD4047BMS consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge triggered monostable multivibrator action with retriggering and external counting options. Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE, RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q, Q, and OSCILLATOR. In all modes of operation, an external capacitor must be connected between C-Timing and RC-Common terminals, and an external resistor must be connected between the R-Timing and RCCommon terminals. Astable operation is enabled by a high level on the ASTABLE input or a low level on the ASTABLE input, or both. The period of the square wave at the Q and Q Outputs in this mode of operation is a function of the external components employed. "True" input pulses on the ASTABLE input or "Complement" pulses on the ASTABLE input allow the circuit to be used as a gatable multivibrator. The OSCILLATOR output period will be half of the Q terminal output in the astable mode. However, a 50% duty cycle is not guaranteed at this output. The CD4047BMS triggers in the monostable mode when a positive going edge occurs on the +TRIGGER input while the -TRIGGER is held low. Input pulses may be of any duration relative to the output pulse. If retrigger capability is desired, the RETRIGGER input is pulsed. The retriggerable mode of operation is limited to positive going edge. The CD4047BMS will retrigger as long as the RETRIGGER input is high, with or without transitions (See Figure 31) An external countdown option can be implemented by coupling "Q" to an external "N" counter and resetting the counter with trigger pulse. The counter output pulse is fed back to the ASTABLE input and has a duration equal to N times the period of the multivibrator. A high level on the EXTERNAL RESET input assures no output pulse during an "ON" power condition. This input can also be activated to terminate the output pulse at any time. For monostable operation, whenever VDD is applied, an internal power on reset circuit will clock the Q output low within one output period (tM). The CD4047BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W
Features
* High Voltage Type (20V Rating) * Low Power Consumption: Special CMOS Oscillator Configuration * Monostable (One-Shot) or Astable (Free-Running) Operation * True and Complemented Buffered Outputs * Only One External R and C Required * Buffered Inputs * 100% Tested for Quiescent Current at 20V * Standardized, Symmetrical Output Characteristics * 5V, 10V and 15V Parametric Ratings * Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Monostable Multivibrator Features
* Positive or Negative Edge Trigger * Output Pulse Width Independent of Trigger Pulse Duration * Retriggerable Option for Pulse Width Expansion * Internal Power-On Reset Circuit * Long Pulse Widths Possible Using Small RC Components by Means of External Counter Provision * Fast Recovery Time Essentially Independent of Pulse Width * Pulse-Width Accuracy Maintained at Duty Cycles Approaching 100%
Astable Multivibrator Features
* Free-Running or Gatable Operating Modes * 50% Duty Cycle * Oscillator Output Available * Good Astable Frequency Stability: Frequency Deviation: - = 2% + 0.03%/oC at 100kHz - = 0.5% + 0.015%/oC at 10kHz (Circuits "Trimmed" to Frequency VDD = 10V 10%
Pinout
C1 R2 R-C COMMON 3 ASTABLE 4 ASTABLE 5 -TRIGGER 6 VSS 7
CD4047BMS TOP VIEW
14 VDD 13 OSC OUT 12 RETRIGGER 11 Q 10 Q 9 EXT. RESET 8 +TRIGGER
Applications
Digital equipment where low power dissipation and/or high noise immunity are primary design requirements
* Envelope Detection * Frequency Multiplication * Frequency Division
* Frequency Discriminators * Timing Circuits * Time Delay Applications
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3313
7-897
Specifications CD4047BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 3 1 2 VDD = 18V Input Leakage Curent (Pin 3) Input Leakage Current (Pin 3) Output Voltage Output Voltage Output Current (Sink) Q, Q, OSC Out Output Current (Sink) Q, Q, OSC Out Output Current (Sink) Q, Q, OSC Out Output Current (Source) Q, Q, OSC Out Output Current (Source) Q, Q, OSC Out Output Current (Source) Q, Q, OSC Out Output Current (Source) Q, Q, OSC Out Output Current (Sink) Output Current (Sink) Output Current (Sink) IIL VDD = 24V, VIN = 11V or GND 3 1 2 IIH VDD = 26V, VIN = 13V or GND 1 2 VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 IOL5RC VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 5V, VOUT = 0.4V 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LIMITS TEMPERATURE +25
oC
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 -300 -10 -
MAX 2 200 2 100 1000 100 300 10 50 -0.53 -1.8 -1.4 -3.5 -0.78 -2 -5.2 -0.7
UNITS A A A nA nA nA nA nA nA nA A nA A mV V mA mA mA mA mA mA mA mA mA mA mA mA mA V
+125oC -55oC +25o C
+125oC -55oC +25oC +125oC -55oC +25oC +125oC +25oC +125oC +25oC, +125oC, -55oC
+25oC, +125oC, -55oC 14.95 +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC
o
0.53 1.4 3.5 0.78 2.0 5.2 -2.8
IOL10RC VDD = 10V, VOUT = 0.5V IOL15RC VDD = 15V, VOUT = 1.5V
Output Current (Source) IOH5RC VDD = 5V, VOUT = 4.6V Output Current (Source) IOH10RC VDD = 10V, VOUT = 9.5V Output Current (Source) IOH15RC VDD = 15V, VOUT = 13.5V N Threshold Voltage VNTH VDD = 10V, ISS = -10A
7-898
Specifications CD4047BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) GROUP A SUBGROUPS 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 +25oC, LIMITS TEMPERATURE +25oC +25oC +25oC +125oC -55oC +125oC, -55oC 3.5 11 1.5 4 V V V V MIN 0.7 MAX 2.8 UNITS V V
PARAMETER P Threshold Voltage Functional
SYMBOL VPTH F
CONDITIONS (NOTE 1) VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND
VOH > VOL < VDD/2 VDD/2
Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) NOTES:
VIL VIH VIL VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
1. All voltages referenced to device GND, 100% testing being implemented 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTES 1, 2) CONDITIONS VDD = 5V, VIN = VDD or GND GROUP A SUBGROUPS TEMPERATURE 9 10, 11 TPHL3 TPLH3 TPLH2 TPLH2 TPHL4 TPLH4 TPLH5 TPLH5 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 400 540 1000 1350 700 945 600 810 500 675 200 270 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER Propagation Delay Astable, Astable to OSC Propagation Delay Trigger to Q, Q Propagation Delay (Note 2) Astable or Astable to Q, Q Propagation Delay (Note 2) Retrigger to Q, Q Propagation Delay (Note 2) Reset to Q, Q Transition Time
SYMBOL TPLH1
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
+25oC +125oC, -55oC
NOTES: 1. VDD = 5V, CL = 50pF, RL = 200K; input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
7-899
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC
o
MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7 -
MAX 1 30 2 60 2 120 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 200 160 350 250 450 300 300 200 200 140 100 80
UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns ns ns ns ns ns ns ns ns ns ns
+125 C VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) VOL VOL VOH VOH IOL5 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V 1, 2 1, 2 1, 2 1, 2 1, 2 +25
oC, +125oC,
-55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125 C -55oC Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC -55 Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2
oC o
+125oC -55 C
o oC
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1, 2
+125
-55oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125
oC
-55oC Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC -55 Input Voltage Low Input Voltage High Propagation Delay Astable, Astable to OSC Propagation Delay Astable or Astable to Q, Q Propagation Delay Trigger to Q, Q Propagation Delay Retrigger to Q, Q Propagation Delay Reset to Q, Q Transition Time VIL VIH TPLH1 VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V TPLH2 TPHL2 TPHL3 TPLH3 TPHL4 TPLH4 TPLH5 TPLH5 TTHL TTLH VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 10V VDD = 15V 1, 2 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
oC
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
7-900
Specifications CD4047BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Q or Q Deviation from 50% Duty Factor SYMBOL QD CONDITIONS VDD = 5V VDD = 10V VDD = 15V Minimum Pulse Width + Trigger - Trigger Minimum Pulse Width Reset TW VDD = 5V VDD = 10V VDD = 15V TW VDD = 5V VDD = 10V VDD = 15V Minimum Retrigger Pulse Width TW VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 7.5 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25 C +25oC +25oC +25oC +25oC +25
oC o
MIN -
MAX 1 1 0.5 400 160 100 200 100 60 600 230 150 7.7
UNITS % % % ns ns ns ns ns ns ns ns ns pF
+25o
C
+25oC +25
oC
+25oC +25 C +25o C
o
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - MSI-1 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 0.2A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
7-901
Specifications CD4047BMS
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTE: OPEN 1, 2, 10, 11, 13 1, 2, 10, 11, 13 1, 2, 10, 11, 13 GROUND 3-9, 12 7 7, 9, 12 7 VDD 14 3-6, 8, 9, 12, 14 4, 5, 14 3-6, 8, 9, 12, 14 1, 2, 10, 11, 13 6, 8 3 9V -0.5V OSCILLATOR 50kHz 25kHz
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V
7-902
CD4047BMS
TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS In all cases External resistor between terminals 2 and 3 (Note 1) External capacitor between terminals 1 and 3 (Note 1) TERMINAL CONNECTIONS FUNCTION ASTABLE MULTIVIBRATOR Free Running True Gating Complement Gating MONOSTABLE MULTIVIBRATOR Positive Edge Trigger Negative Edge Trigger Retriggerable External Countdown (Note 3) NOTES: 1. See text. 2. First positive 1/2 cycle pulse width = 2.48 RC. See note follow Monostable Mode Design Information. 3. Input Pulse to Reset of External Counting Chip External Counting Chip Output to Terminal 4. 4, 14 4, 8, 14 4, 14 14 5, 6, 7, 9, 12 5, 7, 9, 12 5, 6, 7, 9 5, 6, 7, 8, 9, 12 8 6 8, 12 10, 11 10, 11 10, 11 10, 11 tM (10, 11) = 2.48 RC 4, 5, 6, 14 4, 6, 14 6, 14 7, 8, 9, 12 7, 8, 9, 12 5, 7, 8, 9, 12 5 4 10, 11, 13 10, 11, 13 10, 11, 13 TA (10, 11) = 4.40 RC TA (13) = 2.20 RC (Note 2) TO VDD TO VSS INPUT TO OUTPUT PULSE FROM OUTPUT PERIOD OR PULSE WIDTH
Logic Diagrams
C C-TIMING RC COMMON 5 4 6 8 12 9 ASTABLE ASTABLE -TRIGGER +TRIGGER RETRIGGER EXTERNAL RESET MONOSTABLE CONTROL RETRIGGER CONTROL ASTABLE GATE CONTROL LOW POWER ASTABLE MULTIVIBRATOR 3 R 1 2 R-TIMING OSCILLATOR OUT Q FREQUENCY DIVIDER (/2) Q 13 10 11
FIGURE 1. CD4047BMS LOGIC BLOCK DIAGRAM
7-903
CD4047BMS Logic Diagrams
*
ASTABLE ASTABLE +TRIGGER -TRIGGER 5
(Continued) *
RETRIGGER 12 VDD
**
3
RC COMMON
CTC
1
2
RTC
*
4
*
8
*
6 VDD FF1 DQ CL CL R1 R2 OSC OUT 13
VDD 14 VSS 7 VSS
S DQ FF2 CL CL Q R
D Q FF3 CL CL R1 R2
S DQ FF4 CL CL R
10 Q
11 Q
EXTERNAL RESET
*
9 VDD
VDD
**
CAUTION: Terminal 3 is more sensitive to static electrical discharge. Extra handling precautions are recommended.
*
INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS
SPECIAL RC COMMON PROTECTION NETWORK
VSS
FIGURE 2. CD4047BMS LOGIC DIAGRAM
CL R2 R1 p n R1 R2 CL CL p n CL CL CL p n CL Q
CL p n
D D CL CL R1 R2 FF1, FF3 Q
(a)
CL S CL S p n S D CL CL R Q CL p n FF2, FF4 CL R R CL p n Q p D n CL CL CL Q Q
(b) FIGURE 3. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)
7-904
CD4047BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -2.5 0
0 -2.5 -5 -7.5
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-10 -12.5
-10V
-5
-15V
-15
-15V
-7.5
FIGURE 6. TYP. OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
400
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 5V 300
600 SUPPLY VOLTAGE (VDD) = 5V
200 10V 15V 100
400 10V 200 15V
AMBIENT TEMPERATURE (TA 0 20
) = +25oC 100
40 60 80 LOAD CAPACITANCE (CL) (pF)
0
20
40 60 80 LOAD CAPACITANCE (CL) (pF)
100
FIGURE 8. TYP. PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (ASTABLE, ASTABLE TO Q, Q)
FIGURE 9. TYP. PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (+ OR - TRIGGER TO Q, Q)
7-905
CD4047BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns)
(Continued)
4 3 PERIOD ACCURACY (%) 2 1 0 -1 -2 -3 -4 10k 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (VDD) (V) 18 20 10M AMBIENT TEMPERATURE (TA) = +25oC CX = 1F
1M AND 100k 10k 10M
200 SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
RX = 1M AND 100k
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
FIGURE 10. TYP. TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
4 3 PERIOD ACCURACY (%) 2 1 0 -1 10M -2 -3 -4 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (VDD) (V) 18 20 10k 100k RX = 1M 10M 10k 1M 100k AMBIENT TEMPERATURE (TA) = +25oC CX = 0.01F
FIGURE 11. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs SUPPLY VOLTAGE
4 3 PERIOD ACCURACY (%) 2 1 0 -1 -2 -3 -4 0 2 4 6 8 10 12 14 16 SUPPLY VOLTAGE (VDD) (V) 18 20 RX = 1M AND 10k 100k 10k 1M AND 10M 10k AMBIENT TEMPERATURE (TA) = +25oC CX = 1000pF
10k
FIGURE 12. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs SUPPLY VOLTAGE
1 CX = 1F RX = 1M SUPPLY VOLTAGE (VDD) = 5V PERIOD ACCURACY (%) 0 5V
FIGURE 13. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs SUPPLY VOLTAGE
2 CX = 0.1F RX = 1M SUPPLY VOLTAGE (VDD) = 5V
10V, 15V PERIOD ACCURACY (%) 1
10V 0 5V 15V 15V
-1
-2
10V, 15V
-1
10V -3 -55 -2 -15 25 65 105 AMBIENT TEMPERATURE (TA) (oC) 145 -55 -15 25 65 105 145 AMBIENT TEMPERATURE (TA) (oC)
FIGURE 14. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs AMBIENT TEMPERATURE (ULTRA LOW FREQ.)
FIGURE 15. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs AMBIENT TEMPERATURE (LOW FREQ.)
7-906
CD4047BMS Typical Performance Characteristics
2 CX = 0.01F RX = 100k
(Continued)
12 CX = 1000pF RX = 10k
SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V, 10V PERIOD ACCURACY (%) 15V
10 8 6 4 2 0 -2
PERIOD ACCURACY (%)
1
0
5V AND 10V 15V
10V, 15V 10V AND 15V 5V
-1
-2 -55 -15 25 65 105 AMBIENT TEMPERATURE (TA) (oC) 145
-4 -55 -35 -15 25 65 -5 45 85 105 AMBIENT TEMPERATURE (TA) (oC) 125 145
FIGURE 16. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs AMBIENT TEMPERATURE (MEDIUM FREQ.)
RX = 10k SUPPLY VOLTAGE (VDD) = 5V PERIOD ACCURACY (%) 20 100pF 10 0.001F 0.01F, 0.1F, 1F 0 0.001F CX = 100pF -15 25 65 105 AMBIENT TEMPERATURE (TA) (oC) 145 0.01F, 0.1F, 1F
FIGURE 17. TYP. ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs AMBIENT TEMPERATURE (HIGH FREQ.)
8 OUTPUT PULSE-WIDTH VARIATION (%) 6 4 2 0 -2 -4 -6 -8 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) 25 1k 100k 10k RX = 100k, 1M, 10M 10k, 1M AND 10M 1k AMBIENT TEMPERATURE (TA) = +25oC CX = 1F
-10 -55
FIGURE 18. TYPICAL ASTABLE OSCILLATOR OR Q, Q PERIOD ACCURACY vs AMBIENT TEMPERATURE
8 OUTPUT PULSE-WIDTH VARIATION (%) 6 4 2 0 -2 -4 -6 -8 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) 25 10k, 100k, 1M AND 10M 10M RX = 10k, 100k, 1M AMBIENT TEMPERATURE (TA) = +25oC CX = 0.1F
FIGURE 19. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs SUPPLY VOLTAGE
8 OUTPUT PULSE-WIDTH VARIATION (%) 6 4 2 0 -2 -4 -6 -8 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) 25 RX = 1M AND 10 100k 10k AMBIENT TEMPERATURE (TA) = +25oC CX = 1000pF
FIGURE 20. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs SUPPLY VOLTAGE
FIGURE 21. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs SUPPLY VOLTAGE
7-907
CD4047BMS Typical Performance Characteristics
8 OUTPUT PULSE-WIDTH VARIATION (%) 6 4 2 0 -2 -4 -6 -8 -55 -35 0.001F -15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (TA) (oC) 145 0.001F 0.1F 0.01F 0.01F 0.1F RX = 100k SUPPLY VOLTAGE (VDD) = 5V
(Continued)
RX = 100k SUPPLY VOLTAGE (VDD) = 10V OR 15V 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -50 -35 -15 5 25 45 65 85 105 125 145 AMBIENT TEMPERATURE (TA) (oC) 100pF 0.1F AND 0.001F 0.001F 0.01F 0.1F, 0.01F CX = 100pF
FIGURE 22. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs AMBIENT TEMPERATURE
4 10M OUTPUT PULSE-WIDTH VARIATION (%) 2 0 100k -2 -4 -6 -8 1M -10 -12 -55 10M 100k RX = 1M 10k 10k CX = 1000pF SUPPLY VOLTAGE (VDD) = 5V OR 10V
FIGURE 23. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs AMBIENT TEMPERATURE
4 OUTPUT PULSE-WIDTH VARIATION (%) 2 0 -2 -4 -6 -8 -10 -12 10M -35 -15 5 25 45 65 85 105 AMBIENT TEMPERATURE (TA) (oC) 125 145 1M 10M RX = 1M 10k 100k 10k 100k CX = 1000pF SUPPLY VOLTAGE (VDD) = 15V
-35
5 25 45 65 85 105 125 -15 AMBIENT TEMPERATURE (TA) (oC)
145
-50
FIGURE 24. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs AMBIENT TEMPERATURE
105 ASTABLE MODE SUPPLY VOLTAGE (VDD) = 5V 104 C =100pF 10
3
FIGURE 25. TYPICAL OUTPUT PULSE WIDTH VARIATIONS vs AMBIENT TEMPERATURE
106 ASTABLE MODE SUPPLY VOLTAGE (VDD) = 10V POWER DISSIPATION (PD) (W) 105 C =100pF 104 C = 0.01F 103 C = 0.1F C =10pF C =1000pF
POWER DISSIPATION (PD) (W)
C = 0.01F C = 0.1F
C =1000pF
C =10pF 102
101
102
100 10
-1
10
0
10
1
10
2
10
3
10
4
10
5
10
6
101 10-1
OUTPUT PULSE-WIDTH VARIATION (%)
100
101
102
103
104
105
106
Q OR Q FREQUENCY (F) (Hz)
Q OR Q FREQUENCY (F) (Hz)
FIGURE 26. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 5V)
FIGURE 27. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 10V)
7-908
CD4047BMS Typical Performance Characteristics
(Continued)
ASTABLE MODE SUPPLY VOLTAGE (VDD) = 15V POWER DISSIPATION (PD) (W) 105 C = 0.01F 104 C = 0.1F C =100pF C =1000pF C =10pF
103
102
10-1
100
101
102
103
104
105
106
Q OR Q FREQUENCY (F) (Hz)
FIGURE 28. TYPICAL POWER DISSIPATION vs OUTPUT FREQUENCY (VDD = 15V)
Astable Mode Design Information
Unit-to-Unit Transfer Voltage Variations The following analysis presents variations from unit to unit as a function of transfer voltage (VTR) shift (33%-67% VDD) for free running (astable) operation.
TERMINAL 13 t1 t2 t1 t2
Monostable Mode Design Information
The following analysis presents variations from unit to unit as a function of transfer voltage (VTR) shift (33% - 67% VDD) for one shot (monostable) operation.
TERMINAL 8 t1 t2 t1 t2
TERMINAL 13 tA/2 tA tA/2 TERMINAL 10
TERMINAL 10
tM
tM
FIGURE 29. ASTABLE MODE WAVEFORMS VTR ; VDD + VTR typically, t1 = 1.1RC VDD - VTR ; 2VDD - VTR typically, t2 = 1.1RC
FIGURE 30. MONOSTABLE WAVEFORMS VTR ; 2VDD typically, t1 = 1.38RC
t1 = -RC In
t1 = -RC In
tM = (t1 + t2) tM = -RC In (VTR)(VDD - VTR) (2VDD - VTR)(2VDD)
t2 = -RC In
tA = 2(t1 + t2) = -2RC In (VTR)(VDD - VTR) (VDD + VTR)(2VDD - VTR) tA = 4.40RC tA = 4.62RC tA = 4.62RC
where tM = Monostable mode pulse width. Values for tM are as follows: Typ: VTR = 0.5VDD Min: VTR = 0.33VDD Max: VTR = 0.67VDD tM = 2.48RC tM = 2.71RC tM = 2.48RC
Typ: VTR = 0.5VDD Min: VTR = 0.33VDD Max: VTR = 0.67VDD
thus if tM = 2.48RC is used, the variation will be +9.3%, -0% due to variations in transfer voltage.
NOTES: 1. In the astable mode, the first positive half cycle has a duration of tM; succeeding durations are tA/s. 2. In addition to variations from unit to unit, the monostable pulse width varies with VDD and temperature. These variations are presented in graphical form in Figures 19 to 26 with 10V as reference for voltage variation curves and +25oC as reference for temperature variation curves.
thus if tA = 4.40RC is used, the variation will be +5%, -0% due to variations in transfer voltage. Variations Due to VDD and Temperature Changes In addition to variations from unit to unit, the astable period varies with VDD and temperature, Typical variations are presented in graphical form in Figures 11 to 18 with 10V as reference for voltage variations curves and +25oC as reference for temperature variations curves.
7-909
CD4047BMS Retrigger Mode Operation
The CD4047BMS can be used in the retrigger mode to extend the output pulse duration, or to compare the frequency of an input signal with that of the internal oscillator. In the retrigger mode the input pulse is applied to terminal 12, and the output is taken from terminal 10 or 11. As shown in Figure 31 normal monostable action is obtained when one retrigger pulse is applied. Extended pulse duration is obtained when more than one pulse is applied. For two input pulses, tRE = t1 + t1 + 2t2. For more than two pulses, the output pulse width is an integral number of time periods, with the first time period being t1 + t2, typically, 2.48RC, and all subsequent time periods being t1 + t2, typically, 2.2RC. However, in consideration of accuracy, C must be much larger than the inherent stray capacitance in the system (unless this capacitance can be measured and taken into account). R must be much larger than the CMOS "ON" resistance in series with it, which typically is hundreds of . In addition, with very large values of R, some short term instability with respect to time may be noted. The recommended values for these components to maintain agreement with previously calculated formulas without trimming should be: C 100pF, up to any practical value, for astable modes; C 1000pF, up to any practical value for monostable modes. 10k R 1M
External Counter Option
Time tM can be extended by any amount with the use of external counting circuitry. Advantages include digitally controlled pulse duration, small timing capacitors for long time periods, and extremely fast recovery time. A typical implementation is shown in Figure 32. The pulse duration at the output is text = (N - 1) (tA) + (tM + tA/2) where text = pulse duration of the circuitry, and N is the number of counts used.
Power Consumption
In the standby mode (Monostable or Astable), power dissipation will be a function of leakage current in the circuit, as shown in the static electrical characteristics. For dynamic operation, the power needed to charge the external timing capacitor C is given by the following formula: Astable Mode: P = 2CV2f. (Output at terminal No. 13)
AST CD4047BMS Q INPUT PULSE CL CD4017BMS R 11 12
OPTIONAL BUFFER OUT
P = 4CV2f. (Output at terminal Nos. 10 and 11) Monostable Mode:
P= (2.9CV2) (Duty Cycle) T
TEXT
(Output at terminal Nos. 10 to 11) The circuit is designed so that most of the total power is consumed in the external components. In practice, the lower the values of frequency and voltage used, the closer the actual power dissipation will be to the calculated value. Because the power dissipation does not depend on R, a design for minimum power dissipation would be a small value of C. The value of R would depend on the desired period (within the limitations discussed above). See Figures 26, 27, and 28 for typical power consumption in astable mode.
FIGURE 32. IMPLEMENTATION OF EXTERNAL COUNTER OPTION
Timing Component Limitations
The capacitor used in the circuit should be non polarized and have low leakage (i.e. the parallel resistance of the capacitor should be at least an order of magnitude greater than the external resistor used). There is no upper or lower limit for either R or C value to maintain oscillation.
+TRIGGER & RETRIGGER TERMINALS
8 & 12 OSC OUTPUT TERMINAL 13
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
t1 t2
Q OUTPUT TERMINAL 10
tRE
tRE
tRE
tRE
FIGURE 31. RETRIGGER MODE WAVEFORMS
7-910
CD4047BMS Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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